1. Field of the Invention
The present invention is related to a multi-chip stack package structure, and more particularly to a multi-chip stack package structure with metal wires directly connecting to bumps.
2. Description of the Prior Art
In the Information Age in which portable products are successfully developed, users keep seeking high-speed, high-quality, and multi-functional portable electronic products such as laptop computers, 3G mobile phones, PDA, and video game consoles. As far as the outer appearance of products is concerned, the trend is to design portable electronic products lighter, thinner; shorter, and smaller with versatile functions. To fulfill the requirements, the trend of developing multi-chip stack package structure is thus inevitable. In a multi-chip stack package structure, the horizontal package size remains the same but multiple chips are stacked vertically and electrically connected to each other to increase memory capacity or to obtain more functions.
As the manufacturing process advances, the operating speed and bandwidth required by buses between chips in portable systems keep increasing. The speed and bandwidth of system buses are determined by the packaging technology, particularly for System in Package (SiP) in which chips with various functions are encapsulated together. Therefore, the multi-chip stack structure is not only to be designed to have higher transmission speed, shorter transmission path, and better electrical performance, but also to further reduce package footprints and profiles. These features allow the multi-chip stack structures to be prevalently applied in all kinds of electronic products and become mainstream products in the future.
The packaging of multi-chip stack structure, however, is highly challenging when it comes to practical manufacturing process. First of all, as functions of all consumer products advance, higher memory capacity is also required. Therefore, when DRAM of high capacity, for example, a 4 Gb DRAM, is to be manufactured, four 1 Gb DRAMs need to be packaged altogether as shown in FIG. 13A; similarly, eight 1 Gb DRAMs need to be packaged altogether for manufacturing a 8 Gb DRAM. As the number of chips increases, problems may occur for conventional wire-bonded package structures in which metal wires are used to electrically connect the chips, such as lower signal transmission speed or time delay due to the increase of the connection paths or uneven lengths of bonding wires, which will further lead to problems such as system malfunction or data storage errors. Besides, package dimension problem also arises for the conventional wire-bonded multi-chip stack package structures due to bonding wires with the corresponding loop heights. That is to say, the extent of dimension reduction of a multi-chip stack package structure is quite limited, which is a major concern for the conventional wire-bonded chip stack package structures.
In order to solve the aforementioned problems, RDL (Redistribution Layer) is employed to shorten the wire connection paths for multi-chip stack structures and also to effectively overcome the problem of package height, as shown in FIG. 13B. However, high manufacturing cost of RDL has made many producers of high-performance products hang back from incorporating the technology.
Therefore, with the prerequisite of maintaining good electrical performance and the most suitable package size, manufacturing of the multi-chip stack structure with the lowest manufacturing cost has been a major challenge and solutions are eagerly demanded.